SonicRV is an educational platform for web-based simulation and visualization of RISC-V processor architectures. This includes single-cycle, multicycle and pipelined RISC-V processors, which have been derived from the textbook "Digital Design and Computer Architecture, RISC-V Edition" by S. Harris and D. Harris . SonicRV is developed by the Institute for Complex Systems (ICS) headed by Daniel Große, and is used in the computer architecture lecture at JKU.

Explore one of the examples to see SonicRV in action, or keep reading for an overview of its key features.

• Online platform: SonicRV is a web app and has no particular software requirements for users as it runs fully in the browser.
• RISC-V editor: An editor with syntax highlighting for writing assembly programs.
• RISC-V debugger: Step through an assembly program, instruction by instruction, while inspecting it.
• Integrated simulator: Assembly programs may be simulated on VHDL processors with the click of a button. GHDL is used for simulation and our open-source Waveform Analysis Language (WAL) to extract data for visualization.
• Multiple processors: SonicRV is processor agnostic, i.e. any RISC-V processor can be integrated.
• Architectural state: The state of registers and memory is shown for any time point.
• Interactive diagrams: Block diagrams for the processor have been extended to add simulation-specific annotations on demand (e.g. data and adapting color of active components).
• Embedded waveforms: The waveform viewer Surfer is used to display the trace for the executed program.